1. Field of the Invention
The present invention generally relates to a flip-flop circuit and an electronic device including the flip-flop circuit, and more particularly, to a flip-flop circuit which is constructed with CMOS circuits and has a short setup time, a short hold time and a short delay time. The present invention also relates to an electronic device which operates at a high operational speed.
2. Description of the Prior Art
(1) Prior art 1: PA0 (2) Prior art 2 PA0 (3) Prior art 3 PA0 (4) Prior art 4
FIG. 1A shows a schematic diagram of a conventional static-type flip-flop circuit using CMOS circuits. The flip-flop circuit includes inverters 33, 40, 42, 50, 51, 43 and transfer gates 34, 41. FIG. 1B shows a setup time, a hold time and a delay time in the flip-flop circuit shown in FIG. 1A. FIG. 2 shows an example of a configuration of the inverter. In an inverter 104 of FIG. 2, a P-MOS transistor (FET) 105 and an N-MOS transistor (FET) 106 are connected in parallel, and an input signal A is inverted to an output signal Y.
FIG. 3 shows an example of a configuration of the transfer gate. A transfer gate 117 shown in FIG. 3 is constructed with a P-MOS transistor (FET) 118 and an N-MOS transistor (FET) 119 which are connected in series and are driven by complemental clocks (B and /B in FIG. 3, GCK and /GCK in FIG. 1A). When a logic 0 is applied to the P-MOS transistor 118 and a logic 1 is applied to the N-MOS transistor 119, the transfer gate 117 is in a conductive state. When the logic 1 is applied to the P-MOS transistor 118 and the logic 0 is applied to the N-MOS transistor 119, the transfer gate 117 is in an insulating state.
A numeral "/" will be used hereinafter to indicate a reverse signal. For example, a reverse clock /GCK has a reverse phase of that of a clock GCK. Using logical representation, when a state of the clock GCK is 1, a state of the reverse clock /GCK is 0. In general, the clock GCK has the same level transfer timing as that of the reverse clock /GCK. Further, any signal represented by the numeral "/" may have the same function.
In FIG. 1A, a first flip-flop circuit is constructed by returning an output of the inverter 40 to an input of the inverter 40 through the inverter 50 (feedback), and a second flip-flop circuit is constructed by returning an output of the inverter 42 to an input of the inverter 42 through the inverter 51 (feedback).
An output of the inverter 33 is designed so as to have a larger driving ability than an output of the inverter 50. A symbol "*" represents that the inverter has a smaller driving ability, hereinafter.
Therefore, when the transfer gate 34 is in the conductive state, in the first flip-flop circuit constructed with the inverters 40, 50, the output of the inverter 50 is set to the same logic state as that of the output of the inverter 33.
In the same way, the output of the inverter 40 is designed so as to have a larger driving ability than an output of the inverter 51. Therefore, when the transfer gate 41 is in the conductive state, in the second flip-flop circuit constructed with the inverters 42, 51, the output of the inverter 51 is set to the same logic state as that of the output of the inverter 40.
Accordingly, when the transfer gate 34 is in the conductive state (clock GCK=1, reverse clock /GCK=0), an input of the first flip-flop circuit is in the same logic state as that of the output of the inverter 33. After the transfer gate 34 becomes non-conductive, the above state is maintained by the feedback of the inverter 50. In the same way, when the transfer gate 41 is in the conductive state, an input of the second flip-flop circuit is in the same logic state as that of the output of the inverter 40. After the transfer gate 41 becomes non-conductive, the above state is maintained by the feedback of the inverter 51.
In the second flip-flop circuit, for example, in a case that the output of the inverter 40 is at a high level H and the output of the inverter 51 is at a low level L, when the transfer gate 41 becomes conductive by the clocks GCK, /GCK, the output of the weakly driving inverter 51 is transferred to the high level H by the output of the strongly driving inverter 40. And the outputs OUT, /OUT are changed by the inverter 42. A time interval from when the clocks GCK, /GCK are applied to the transfer gate 41 until the outputs OUT, /OUT are changed is associated with a delay time of the flip-flop circuit.
Next, a description will be given of the setup time and the hold time in the flip-flop circuit shown in FIG. 1A, by referring to FIG. 1B. In the first flip-flop circuit, when the clock GCK transits from the high level to the low level, the transfer gate 34 goes from being conductive to non-conductive.
When the clock GCK is at the high level so that the transfer gate 34 is conductive, if the input DIN changes, for example, from the high level to the low level, as shown in a transition (1), first the outputs of the inverters 33, 50 compete with each other. And next, the feedback loop circuit consisting of the inverters 40, 50 operates to stabilize the output of the inverter 40. If the transfer gate 34 becomes non-conductive by the clock GCK becoming the low level after the feedback loop is almost stabilized, the low level of the input DIN is taken into the first flip-flop circuit. The setup time is a minimum time period from the transition of the input DIN to the transition of the clock GCK in the condition that the feedback loop consisting of the inverters 40, 50 is almost stabilized before the transition of the clock GCK. Namely, the setup time approximately corresponds to a period for the competitions between the outputs of inverters 33, 50 and the stabilization of the feedback loop consisting of the inverters 40, 50.
When the input DIN changes as shown in a transition (2) just before the clock GCK becomes the low level, first the outputs of the inverters 33, 50 compete with each other. And next, the feedback loop circuit consisting of the inverters 40, 50 operates to stabilize the output of the inverter 40. However, if the transfer gate 34 becomes non-conductive by the clock GCK becoming the low level before the feedback loop is almost stabilized, the low level of the input DIN is not taken into the first flip-flop circuit. Namely, a state of the first flip-flop circuit which was set by the high level of the input DIN may be held, even if the input DIN changes. The hold time is a maximum time period from the transition of the input DIN to the transition of the clock GCK in the condition that the feedback loop consisting of the inverters 40, 50 is little stabilized at the transition of the clock GCK.
In a gray zone which is represented by subtracting the hold time from the setup time, the low level or the high level of the input DIN may certainly be taken into the first flip-flop circuit.
In the above operation, when the outputs of the inverters 33, 50 compete with each other, the setup time and the hold time respectively are increased. The increase in the setup time and the hold time makes it difficult to increase the operation frequency of the flip-flop circuit.
In general, master/slave-type flip-flop circuits are widely used in the CMOS circuits. The above operation of the first flip-flop circuit is for the master-side flip-flop circuit. The second flip-flop circuit on the slave side operates the same as the first flip-flop circuit. When the output of the inverters 41, 51 compete with each other, the setup time and the hold time of the second flip-flop circuit may also increase.
In general, to improve an efficiency in examining data of an LSI circuit, a SCAN circuit is added to a flip-flop circuit. In the flip-flop circuit, a large number of logic states in the flip-flop circuit are controlled from a SCAN input of the SCAN circuit, and the logic states in the flip-flop circuit are read out from a SCAN output.
FIG. 4 shows a schematic diagram of the flip-flop circuit shown in FIG. 1A which includes the SCAN circuit and an additional reset circuit. In FIG. 4, an input /RST is a signal to reset the flip-flop circuit to an initial state. An input SIN is a signal to forcibly set a state of a flip-flop circuit consisting of an inverter 54 and a NAND circuit 68 to a state determined by the input SIN in response to a clock ACK for examination of the flip-flop circuit when a transfer gate 53 is in the non-conductive state.
In the flip-flop circuit shown in FIG. 4, to add the reset circuit, a circuit for the feedback loop in a first flip-flop circuit including the inverter 54 is changed from an inverter to the 2-input NAND circuit 68. A configuration of the 2-input NAND circuit 68 may be as shown in FIG. 5. And also, an inverter corresponding to the inverter 42 shown in FIG. 1A is changed to a 2-input NAND circuit 57 to add the reset circuit. A reset signal is applied to the flip-flop circuit so as not to cause a conflict in polarity at each point of the flip-flop circuit.
In general, in a CMOS integrated circuit, a large number of such flip-flop circuits as shown in FIG. 4 are used and are connected in series like a chain. For example, they are connected such that an output /OUT of a 1st flip-flop circuit is connected to an input SIN of a 2nd flip-flop circuit, an output /OUT of the 2nd flip-flop circuit is connected to an input SIN of a 3rd flip-flop circuit, etc.
Further, in the flip-flop circuit shown in FIG. 4, a transfer gate 55 controlled by clocks BCK, /BCK is added. When the flip-flop circuit is used for a normal operation of a system, the transfer gate 55 is maintained to be conductive. When the flip-flop circuit is examined, a transfer gate 65 and the transfer gate 55 becomes alternately conductive and non-conductive so as not to cause a racing condition (condition in which data overtakes the clock without synchronizing to the clock). An examined signal is sequentially shifted through the chained inputs SINs.
FIG. 6 shows a schematic diagram of a modification of the flip-flop circuit shown in FIG. 1A. In the flip-flop circuit shown in FIG. 6, transfer gates 44, 46 are added to the flip-flop circuit shown in FIG. 1A to respectively prevent the inverters 33, 45 and the inverters 40, 47 from competing with each other. The flip-flop circuit further includes a clock generation circuit having an inverter 39, which generates the complementary clocks /GCK, GCK from a system clock /CLK.
In the flip-flop circuit shown in FIG. 1A, as mentioned before, the inverters 33, 50 and the inverters 40, 51 respectively compete with each other. However, in the flip-flop circuit shown in FIG. 6, since the transfer gate 44 is operative in the reverse clock phase against the transfer gate 34, the inverter 33 and the inverter 45 alternately exclusively control the input of the inverter 40. In the same way, since the transfer gate 46 is operative in the reverse clock phase against the transfer gate 41, the inverter 40 and the inverter 47 alternately exclusively control the input of the inverter 42.
The clocks GCK, /GCK are generated in the clock generation circuit shown in FIG. 6. However, there is a slight phase shift between the clock /GCK and the inverted clock GCK through an inverter 39. Thus, a short period of competition between the inverters 33, 45 may be caused, which competition effects the delay time of the flip-flop circuit.
FIG. 7 shows a schematic diagram of a modification of the flip-flop circuit shown in FIG. 1A. The flip-flop circuit except a clock generation circuit consisting of a NOR circuit 48 and an inverter 49 is the same as the flip-flop circuit shown in FIG. 6. In the clock generation circuit shown in FIG. 7, a control input INH for gating the system clock /CLK is included. Gating the system clock /CLK is carried out by using the 2-input NOR circuit 48. A configuration of the 2input NOR circuit 48 may be as shown in FIG. 8. In a computer control system, the clocks may be controlled for each flip-flop circuit. The above control input INH is used for such purpose.
FIG. 9 shows a schematic diagram of the flip-flop circuit shown in FIG. 7 which further includes the SCAN circuit and the additional reset circuit. The SCAN circuit and the reset circuit are operative in the same way as that of the circuits shown in FIG. 4. In FIG. 9, a clock generation circuit for generating the clocks ACK, /ACK, and a clock generation circuit for generating the clocks BCK, /BCK are also represented as portions of the flip-flop circuit. Timings of these clocks to the respective transfer gates are the same as those in the flip-flop circuit shown in FIG. 7.
FIG. 10 shows a schematic diagram of a modification of the flip-flop circuit shown in FIG. 7. In the flip-flop circuit shown in FIG. 10, an inverter 79 is connected with an output of an inverter 78 to produce an output OUT of the flip-flop circuit from the inverter 79. Other operations are the same as those of the flip-flop circuit shown in FIG. 7.
FIG. 11 shows a time chart indicating an operation of the flip-flop circuit including the SCAN circuit shown in FIG. 4 or FIG. 9. In FIG. 11, after the flip-flop circuit is reset by a negative reset pulse /RST, a first rising edge of the clock /CLK is masked by the control signal INH of the high level to stop a clocking operation. After the control signal INH becomes the low level, the input data DIN of the high level is taken by a second rising edge of the clock /CLK, and the input data DIN of the low level is taken by a third rising edge of the clock /CLK.
Before performing the SCAN operation, the clock BCK is set to the low level. After that, the scan-in-data SIN of the high level is taken into the flip-flop circuit by the clock ACK. By the next exclusive clock BCK, the scan-in data SIN arrives at the output OUT.
FIG. 12 shows a schematic diagram of a conventional dynamic flip-flop circuit. The dynamic flip-flop circuit is constructed with transfer gates 34, 36 and inverters 33, 35, 37, 38, 39. A capacitor may be connected to an input of the inverter 35 to hold a signal at its node. It is well known that a cell of a dynamic RAM (DRAM) is similar to the above flip-flop circuit, and is constructed with two elements, one MOS transistor for switching and one capacitor for holding data.
In FIG. 12, when the transfer gate 34 is in the non-conductive state, a logic state at the input of the inverter 35 is maintained for a certain time according to the capacitance added to the input. By an such operation, a flip-flop function is realized.
FIG. 13 shows a variation of a voltage at a node, which voltage level is to be held in the flip-flop circuit. As shown in FIG. 13, the level voltage to be held with the capacitor may be degraded due to a leakage, etc., after a length of time.
In the above-mentioned DRAM, in general, the data is held by a refresh operation which stores the data repeatedly at a time interval.
In the dynamic flip-flop circuit shown in FIG. 12, there is no competition between the outputs of the inverters unlike in the flip-flop circuit shown in FIG. 1A. And no delay time due to the feedback loop is caused. Therefore, the dynamic flip-flop circuit has an extremely good performance for the delay time, the setup and hold times. However, it is difficult to hold the data for a long time without using the refresh operation in the DRAM.
In a system operation of circuits including the flip-flop circuit, there are some cases that sequential high-frequency clocks are not applied to the flip-flop circuit. The cases are, for example, i) the clock is masked by the control input INH so as not to be applied, ii) a low-frequency clock having a 50% duty cycle is used in a system setup test, and iii) low-frequency clocks ACK, BCK are used for a test operation. In such cases, the dynamic flip-flop circuit shown in FIG. 12 cannot be used.
As mentioned above, in the flip-flop circuits shown in the above-mentioned prior arts (1), (2), the outputs of the inverters compete with each other and it takes a long time to stabilize the feedback loop. Therefore, there is a problem that the setup time and the hold time are increased.
In the flip-flop circuit shown in the prior art (3), when there is a time delay between the clock /GCK and the clock GCK, a short competition between the outputs of the inverters is caused. Further, there is a problem that a number of circuit elements constructing the transfer gates, etc., is large, and a circuit configuration becomes complex.
In the dynamic flip-flop circuit shown in the prior art (4), there is a problem that it is difficult to use the dynamic flip-flop circuit in the low-frequency operation.